The present invention relates to the formation and filling of interconnects within electronic components such as printed circuit boards and integrated circuits.
With changes in sophistication of electronic equipment over the years, manufacturers of electronic component packages have produced higher density circuits in smaller packages. High interconnect density on electronic component packages is provided by utilizing multi-layer circuits separated by a dielectric material. The demand for manufacturing semiconductor IC devices such as computer chips with high circuit speed, high packing density, and low power dissipation requires the downward scaling of feature sizes in ultra-large-scale integration (ULSI) and very-large-scale integration (VLSI) structures. This demand presents an acute challenge to retain and advance the integrity of the prior-generation electronic component packages while dramatically increasing the processing capability of the circuitry.
In general, electronic component packages are manufactured using conductive traces on the surface, or X-Y plane, of the electrical circuit's substrate to connect discrete electronic devices. Distinct layers of the package are vertically connected by through-hole interconnects, or vias. Conductive vias are traditionally created by drilling though a stack of circuit substrate layers, then plating the wall of the via with an electrically conductive material. Such multi-layered circuits may contain as many as 100-200 vias per square inch (15-30 per square centimeter).
In the continuing effort to shrink the size of electronic component packages and increase the density of electronic components in a given package, microvias having a diameter of less than about 1 mil (25 microns) have been created by laser machining, plasma etching, or photolithography.
As an alternative to plating of metal into interconnects, monomer paste is often used to fill interconnects. After interconnects are formed, a pattern is laid over the workpiece and a screen-printing or stenciling process forces filler paste into the interconnects. A stencil or other masking device is required to prevent the paste from contacting the substrate surface other than the interconnects, because filler material is difficult to remove from the substrate surface and can compromise the electrical properties thereof. These processes require fine dimensional alignment of holes in a stencil with the interconnects, with is increasingly difficult as the industry moves toward smaller and smaller interconnects, or microvias. Moreover, there can be difficulties ensuring sufficient fill characteristics of the interconnects. These concerns are compounded as the workpiece increases in size or in interconnect density by the tendency of the workpiece's dimensions to change, even slightly, during processing.
Once an interconnect is filled with the paste, the workpiece is subjected to a thermal treatment, which cures the paste by initiating a polymerization process. The paste undergoes appreciable shrinkage during the polymerization process, resulting in depressions where the cured interconnect fill material shrinks and is no longer coplanar with the substrate surface. Such depressions may trap processing materials in the interconnect such as, for example, flux or cleaning chemicals, compromising the electrical integrity of the electronic component package.